Power Integrity Engineer

Job Description
You will be responsible for providing package and platform power integrity solution for SoC ingredient targeted from tablet, laptop mobile devices to desktop. In this position, you are required to architect package and board power integrity solution such as voltage rail merging and isolation scheme, stackup and decoupling cap type and to provide design constraints for and guide implementation of component packages and boards to meet power noise targets. You will also be focusing on design processes, techniques including electrical model extraction, development and simulation from DC to high frequency component on full system encompassing voltage regulator, board, package, silicon and decoupling or filtering. End goal is to deliver optimized platform electrical solution on a first-time right physical design within the boundary condition followed by design validation and correlation for continuous methodology enhancement.

Qualifications

- Bachelor Degree or higher in Electrical/Electronic Engineering: - relevant experience in silicon, package and board level power integrity design- Familiar with electrical simulation software such as Sigrity PowerSI, PowerDC, HSpice, Matlab.- Familiar with package/board CAD tools such as Cadence Allegro and Mentor Graphics.- Knowledge in platform system architecture, I/O structures & topologies are added advantage.

Inside this Business Group

The Client Computing Group is responsible for all aspects of the client computing business across Phone, Phablet, Tablet and PC platforms, leading Intel's efforts to transform client computing through technologies, new form factors, and driving Intel's corporate-wide user experience initiatives. This spans all client device brands including hardware, software and connectivity ingredients for phones, tablets, Ultrabook™, All-in-Ones, 2 in 1 computing devices, and home gateways.