Inside this Business Group
Bachelors/Masters/PhD in Computer Science/Electrical/Electronic Engineering.
Knowledge in C/C++, SystemVerilog, Python, IA, SoC Architecture, UPF and Low Power Flows
Understanding of synthesis and timing analysis flow with involvement in at least one SoC/sub-system design tape-out.
Hands-on experience in silicon/FPGA/emulation debug, RTL validation or Power/Performance validation is a plus.
Experience in Emulation, Altera/Xilinx/Synopsys/Mentor/Cadence Tools Flow, HAPS is a plus.
Should have strong communication, analytical skill and a good team player.