Within Infrastructure Platform Solutions Group (IPSG), the Mixed-Signal IP solutions Group MIG is chartered with delivering timely, competitive and reusable mixed-signal IP for Plug-n-Play in an IP subsystem or SOC and its platform. We create I/O designs for Intel products that service server, client, chipset, modem and IOT markets.
The MIG Release Engineering team is a dynamic and versatile team of engineers managing a variety of release management and quality assurance activities for all mixed-signal IPs.
In this role, you will -
-Handle release & QA for mixed-signal IPs like Memory PHY and HSIO IPs (eg. DDR4/LPDDR4, PCIe3/4, USB3.1, ThunderBolt etc.) and do releases for internal SoC customers/partners
-Automate build, test, integrate, and release processes and evaluate risk of issues affecting upcoming releases, as well as risk of proposed fixes.
-Develop strategies for improving and simplifying build release process, investigate tools and processes and integrate them to enable delivery on a predictable and consistent schedule.
- Manage release branch and investigate and address integration, build, and other technical issues and enhance and improve QA suite to ensure integrity and quality of collateral deliverables.
-Develop cross-functional processes for coordinated release management and partner with engineering and program mgmt. teams.
Inside this Business Group
-B.S./M.S. with 5+ yrs of experience in relevant field
-Self-motivated, proactive, able to work independently and demonstrate creative and critical thinking capabilities
-Exceptional verbal and written communication skills; capable of collaborating and brainstorming with technical staff
-Build and Release Engineering/Release management work experience
-Working knowledge with version control tools such as perforce etc., build automation, makefiles and unix programming/scripting in perl, shell scripts etc.
-Experience in one of the following areas is a plus: logic design/validation, circuit design/validation, mixed signal validation