ACES department (Architecture, Circuits, Ethernet and SerDes IP’s) is looking for Pre-Silicon verification Engineer.
ACES develops and delivers PLL’s and all High Speed networking and communication building blocks (as Ethernet PHY, PCIE, USB-TypeC, DP/HDMI) to all Intel devices (Client and Servers CPU’s / Chipset / Controllers). Team delivers state of the art technologies as 112G and higher Ethernet PHY in Intel process (14nm/10nm/7nm).
We're looking for engineers for Ethernet PHY pre-silicon verification team located in Jerusalem.
In this role you will deal with all the verification phases along the project, from learning the specs and the design, defining environment and test plan, implementing the environment and run & debug simulations.
The team is also taking part in the post-silicon validation effort in the lab.