Staff Physical Design Engineer
Creates bottomsup elements of chip design including but not limited to FET, cell, and blocklevel custom layouts, FUBlevel floor plans, abstract view generation, RC extraction and schematictolayout verification and debug using phases of physical design development including parasitic extraction, static timing, wire load models, clock generation, customer polygon editing, autoplace and route algorithms, floor planning, fullchip assembly, packaging, and verification. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. Schedules, staffs, executes and verifies complex chips development and execution of project methodologies and/or flow developments. Requires expansive knowledge and practical application of methodologies and physical design.
Inside this Business Group
Degree in Electrical or Electronic Engineering with minimum 4+ years in VLSI physical layout design.
Experience in high-speed custom layout in 14nm and 10nm process node. Technical experience in hands-on Analog Custom Layout, proficient in floor planning, extraction, layout optimization and verification. Understanding of ESD (Electro Static Discharge), EM (Electro Migration) and DFM (Design for Manufacturing).
Experience with industry standard tools for Analog such as Cadence Virtuoso would be an advantage