In this position you will be part of a world class SoC design team responsible for design and development of the Graphics SOCs part of the Core & Visual Computing Group. This is a great opportunity to join a talented team and will include lots of product innovation on cutting edge technologies.
Your responsibilities will focus on the RTL to GDS flow and may include but not be limited to:
* Constraint understanding, generation, clock stamping and timing closure
* Synthesis with Synopsys Design Compiler DCT
* DFT, Scan Insertion, and coverage analysis
* Multiple Power Domain Analysis using standard Power Formats UPF/CPF
* Place and Route and clock tree synthesis with Synopsys ICC2
* Static Timing Analysis with Synopsys Primetime
* Formal equivalence
* Layout Verification and DRC analysis
The ideal candidate should exhibit behavioral traits that indicate:
* Self-motivator with strong problem solving skills
* Strong leadership skills with ability to mentor junior designers
* Excellent interpersonal skills, including written and verbal communication
* Ability to work as part of a team and collaborate in a high-paced atmosphere
* Ability to provide technical direction to the team and influence project execution and methodology
Master's/Bachelor's Engineering Degree in field of Electrical, Electronics, Computer Science
3 - 15 years of PD experience in back-end design and/or integration
Experience in 16/14/10/7nm a process is a must
Demonstrated ability to work with RTL and DFT teams.
Demonstrated ability in productizing scripts for use by team/project
The Core and Visual Computing Group (CVCG) is responsible for the architecture, design and development of the CPU core and visual technology IPs that are central to Intel's system-on-a-chip (SoC) products and key to our datacenter, client and Internet-of-Things (IOT) platforms. CVCG strives to lead the industry through continuous innovation and world class engineering.