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Job ID: JR0089815
Job Category: Engineering
Primary Location: Leixlip, IE
Other Locations:
Job Type: College Grad

Movidius DFT engineer

Job Description

The Movidius team in Leixlip (Ireland) are looking for experienced designers in the area of RTL design, SystemVerilog/OVM Verification, scan methodologies in the area of DFX (Design for Test/Debug/Manufacturability/Reliability) to help drive innovation in our product line into these exciting new areas.  

As part of the team you will be essential in helping Intel bring these dreams to reality.  You will be part of a dynamic team that values everyone’s opinion and collaborates to develop the best solutions to the world’s problems. 

You will play an integral role in delivering new market-leading features for product and solution releases whilst working closely with the Architecture, SoC Security, RTL, Verification, Physical and Manufacturing teams to ensure the design will achieve right-first-time silicon in high volume production.

Other responsibilities include:


* Using SoC knowledge of RTL, Verification and Physical design to drive DFX design implementation

* Architecting and implementing leading edge RTL features for DFX

* Designing and implementing SoC level SystemVerilog/OVM test benches

* Creation and implementation of the test plans, scan strategy, MBIST and silicon debug

* Troubleshoot a wide variety of functional issues using all the features of DFX in order to apply proactive intervention (e.g. test coverage analysis, test pattern generation and interfacing with manufacturing test team)



Required Experience

* Hons. Bachelors/Masters in Electronic Engineering /Computer Science or equivalent

* In depth knowledge of DFT concepts 

* In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis 

* Proficient in RTL implementation and simulation, ideally using Verilog and VCS

* Proficient in verification methodologies - SystemVerilog/OVM/UVM/VMM/Specman

* knowledge of equivalence check, DFT DRC rules both In RTL lint tool (spyglass) and ATPG tool (TetraMax/Fastscan)

Desired Experience

* Knowledge of SoC project lifecycles from architecture, RTL, verification to GDSII 

* Good design for test knowledge with design experience

* Knowledge of JTAG protocol, Boundary Scan, TAP networks, scan methodologies, BIST techniques(SMS/Tessent Shell)

* Working experience in Synopsys Tetramax and Synopsys SMS BIST is a plus

* Analogue DFT experience (e.g. ADC, DAC etc.)

* Understanding of IEEE 1687 (IJTAG)

* Hierarchical scan knowledge (CTL)

* Tcl/Tk/Perl to automate design process and improve efficiency

* Knowledge of Synthesis/Scan stitching, STA, ATPG and MV design an advantage 

* Knowledge of Synopsys DC/DFT Compiler, Primetime and UPF an advantage

Inside this Business Group

The Corporate Strategy Office is chartered to support the executive office in driving corporate initiatives, including near and long-term strategy, major cross-group decision making and ensuring cross-company alignment.  To deliver to that mission, the team owns shaping, driving and synthesizing insights to directionally orient trends as well as long range strategic planning/visioning , cross company alignment and greenfield innovation.  Communications are essential to drive alignment so there is a focus on communications, community and acumen development.  The team is ccommitted to ensuring that Intel efforts are aligned to, and actively driving success toward the most impactful business strategies.

IECollege GradJR0089815
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