In this position you will be part a world class SoC physical design team focusing on high end products based on GP-GPU/GFX targeting applications such as Graphics, Gaming, Artificial Intelligence, Media processing, Autonomous Driving and more. You will be responsible for but not limited to Static Timing Analysis(STA) and timing closure of multi-million gate SOC designs in advanced process nodes 10nm or later brining in differentiation to push the performance targets. You will be working closely with SOC architects and design team to understand the timing specifications , clocking architecture , DFX architecture, external interface AC timing requirements, etc. As part of the SOC timing closure, you will be working closely with Place & Route engineers to provide timing budgets , placement guidelines and support partition level timing signoff.
- Experience Timing & Noise Signoff at block level or Full chip level on advanced process nodes.
- Should have a clear understanding of Crosstalk delay/noise, Timing derates, AOCV/POCV concepts and its impact of design closure
- Should have worked on Timing ECO generation in multi-voltage designs.
- Experience with Industry Timing signoff tools like Primetime / Tempus is a must.
- Team player, with good problem solving and communication skills
- Automation skills in PERL and/or TCL and/or Shell* is an added plus.
Mtech/Btech in the fields of electrical/electronic/computer engineering/science with 6 to 10+ years of experience in Static Timing Analysis (STA)Inside this Business Group
The Core and Visual Computing Group (CVCG) is responsible for the architecture, design and development of the CPU core and visual technology IPs that are central to Intel's system-on-a-chip (SoC) products and key to our datacenter, client and Internet-of-Things (IOT) platforms. CVCG strives to lead the industry through continuous innovation and world class engineering.