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Qualification: Mtech/Btech in the fields of computer engineering/science with 6+ years of experience in areas of Physical design, APR and signoff flows designing chip level or block level layouts in advanced process nodes. Sound knowledge in RTL to GDSII Implementation flows in areas of Logic synthesis, floor planning, power planning, placement, CTS, routing, timing sign-off, fill, layout verification etc. Require expertise in design optimization for Power, Performance & Area improvements leading to reduction in die size reduction or improved landing zone for the SoC. Experience with Low power design closure UPF based implementation and associated sign-off SG-LP/VCLP/Conformal methods is added plus. EDA tool knowledge: Design Compiler, ICC/ICC2 is preferred. Should be a Team player, with good problem solving and communication skills. Automation skills in PERL and/or TCL and/or Shell* is an added plus.
The Core and Visual Computing Group (CVCG) is responsible for the architecture, design and development of the CPU core and visual technology IPs that are central to Intel's system-on-a-chip (SoC) products and key to our datacenter, client and Internet-of-Things (IOT) platforms. CVCG strives to lead the industry through continuous innovation and world class engineering.