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Job ID: JR0083201
Job Category: Engineering
Primary Location: Bangalore, KA IN
Other Locations:
Job Type: Experienced Hire

Full Chip Timing Engineer

Job Description
In this position, you will be responsible for all aspects of STA & timing
closure activities of Intel's SoCs in lower technology nodes. Your tasks
will include but not limited to:


Design & Architecture understanding, Interaction with FE/DFT/Verification
teams, Clocking, Constraints development, ACIO Timing, Understanding
synchronous & asynchronous paths, Clock domain crossing issues,
Understanding and debugging extraction issues, Deciding timing signoff
modes & corners, Design margins, Hierarchical timing including IO budgeting
for partitions, Drive the designs to timing closure, interacting/supporting
synthesis and APR team during timing closure cycle, timing ECOs, Timing
model build, Timing signoff & quality checks.

You will also be part of debug/troubleshoots for a wide variety of tasks up
to and including difficult/critical design issues and proactive
intervention, as required.


Qualifications

Education: B.Tech. or M.Tech. in Electrical/Electronics Engineering with 4
to 8 year's experience.

Preference: Master's Degree in Electrical/Electronics Engineering with
VLSI/microelectronics specialization, with 4 to 8 years of experience in
STA.

*Key Skills:*

- In-depth knowledge & hands-on experience with the overall silicon
implementation flows and methodologies such as STA, Synthesis, Clocking is
required. Good understanding & exposure of overall Timing closure cycle in
SoC.

- Good scripting skills in TCL/Perl/Shell. Expertise in STA signoff tools
(PT/ETS).

- Skill in Synopsys tools (PT/DC) & exposure to ICC will be an added
advantage.

- Solid understanding of the process and design interactions as they relate
to the target frequency and interaction with timing paths and resulting leakage
and power trade-offs.

- Solid technical and good communication skills.

- Good team player

Inside this Business Group

INExperienced HireJR0083201
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