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Job ID: JR0082930
Job Category: Engineering
Primary Location: Bangalore, KA IN
Other Locations:
Job Type: Experienced Hire

Physical Design and Verification Engineer

Job Description
The candidate will be responsible for implementing and validating the DFX for complex SoC designs in 10nm and less processes for the Technology `and Platform Development group.


B.Tech/M.Tech in Electronics/Electrical/Computer engineering and 6-8 years of experience. Should have worked on Scan chain insertion, EDT implementation and verification. Should have generated and validated at-speed, path-delay and Ram-sequential ATPG patterns. Should be able to write custom MBIST Algorithm which could be ported in Tessent-PMBIST flow Should have performed ATPG timing simulations.Should have implemented Bscan and Tap network IEEE1149.7,Post-si debug experience is a plus Strong interpersonal skills, debug skills, TCL/perl script knowledge and good verbal/written communication skills are required.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth

INExperienced HireJR0082930
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