In this position, the candidate will be responsible for design of soft IP cores for Intel's next generation chips (including SOCs) for the different market segments.
Design Lead will be responsible for the execution and quality of at least 2 IPs and will sign off all design checks and interact with SOC for all integration issues
Master of Science (or a Master of Technology) degree in Electrical Engineering with more than ten years of relevant industry experience or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than twelve years of relevant industry experience.
Experience : Relevant ASIC design/validation experience in front end processes including RTL development, functional and performance verification
Expertise in design, development and integration of design blocks (IP) for system-on-chip (SoC) components
Expertise in verilog and system verilog based logic design
Experience in all design tools like linting, DC, CDC, LEC
Expertise in DFX
Experience in one/more of the following areas PCIe, USB, DP and /or AMBA standards (OCP, AXI, AHB etc..)
Knowledge of SVA
Knowledge of considerations for performance, power and cost optimization is desirable