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Job ID: JR0045839
Job Category: Engineering
Primary Location: Santa Clara, CA US
Other Locations: US, Idaho, Boise;
Job Type:

OPC/Mask Development Engineer

Job Description


The Intel NVM (Non Volatile Memory) Process Technology Development group is responsible for developing state of the art technologies like 3D-NAND and 3D-Xpoint. In this leadership role in the area of Mask/OPC development, you are expected to drive key aspects of post database release activities.  You will be chartered with developing, coding and maintaining mask and OPC algorithms and will be involved in prep work of the mask data prior to tape-out of reticles for current and future NVM technologies.

Responsibilities include, but are not limited to:

  • Coding and maintaining of mask synthesis and OPC algorithms for modification and validation of GDS2/OASIS data to specifications provided by the technology development engineers,
  • Understand and drive process/reticle/layout interaction requirements
  • Write clear concise code in Calibre and Hercules without errors. Experience in any other languages like C, C++ acceptable.
  • Document and present code in Generator/Tape out reviews sessions
  • Write pattern matching checks for complicated layouts which are required for High Volume manufacturing.
  • Write fill code and optimize algorithms to pass density and DFM flows.
  • Interface with multiple other groups like Process Integration, Design Rules, CAD, Layout, Scribe and Mask shops
  • Drive projects across multi-disciplinary teams focusing on layout and mask generation, litho or code issues.
  • Drive diagnostic projects across x-functional teams to understand product and test structure failures and their interaction with layout and mask synthesized data.



  • Knowledge of Calibre, Hercules or any other languages like C, C++ in Linux.
  • Understanding of scripting languages like Perl & Python helpful.
  • Familiarity of Tape-out, OPC and Mask Generation Flows for High volume manufacturing
  • Good understanding of GDS2/SF/OASIS format & layout hierarchy & layer maps.
  • Knowledge of DFII, K2VIEW and other Industry standard CD capture/measurement tools.
  • Good verbal & written communication skills with Excel, Visio & Power Point proficiency.


  • BS/MS in EE, Physics, Computer Science, Material Science or Chemistry.
  • At least 5 years relevant industry experience in OPC/Mask/CAD.


  • Santa Clara ,CA or Boise, Idaho

Inside this Business Group

Employees in Intel's NVM Solutions Group deliver solutions that are transforming computing across all segments from data centers to Ultrabooks. They invent, develop, bring to market and support customers with leading-edge NAND flash memory and system level solutions such as solid state drives (SSDs). SSDs are accelerating performance for gaming enthusiasts, reducing total cost of ownership for IT managers of data centers and improving security and reliability for businesses. This dynamic group is strategically positioned to become the leading Non-Volatile Memory solution supplier for the compute segment and is a key to expanding markets and continuing the growth for Intel.

Other Locations
US, Idaho, Boise;

Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.

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