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Job ID: JR0050241
Job Category: Engineering
Primary Location: Santa Clara, CA US
Other Locations:
Job Type:

Low Power Design Engineer

Job Description

Join Intel as part of the BaseBand & SoC Development group in iCDG (Intel's Communication and Devices Group). We are looking for experienced Low Power Design Engineers.

In this position you will contribute to the development of application specific processors for Intel's multimode cellular modems.

Your responsibilities will include but are not limited to:

This candidate is responsible for Complex SoC low power design, analysis and implementation for Modem Products.

  • Develop Design specifications
  • Low power digital design
  • IP integration
  • DV support
  • Running tools like lint, CDC to clean the design
  • Understand Synthesis and Timing constraints


MSEE with 5+ of experiences in ASIC Low Power related design

  • Experience with lower design in advance process nodes
  • SoC power management design experience

Preferred Requirements

  • Proficiency in ASIC design with 5+ years of directly related experience
  • Block level and SoC level power related design verification experience is a plus
  • Understanding of ASIC low power design techniques, understand UPF, NLP simulation debug
  • Proficient in Shell and Perl scripting, Python skills are a plus
  • SoC level clock design experience is a plus
  • System level architecture knowledge is a plus


Inside this Business Group

Intel is one of the largest suppliers of chips for the communications market. The Intel Communications group is focused on designing and building communications technologies such as Ethernet connectivity products, optical components, communications processing solutions and broadband products.

Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
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