You will be part of the world class SoC physical Integration and Design team within the Scalable Performance CPU Development Group SDG working on next generation Xeon Server CPUs
Your responsibilities will include but not be limited to:
The ideal candidate will be able to demonstrate the following behaviors:
BS degree in Electrical Engineering, Computer Engineering or other related field of study with a minimum of 8+ years of relevant experience in SOC/IP physical design or MS degree with 5+ years or PHD with 5+ years of direct related experience with SOC Physical design and Static Timing Analysis
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.