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Job ID: JR0035640
Job Category: Engineering
Primary Location: San Diego, CA US
Other Locations: US, California, Santa Clara;
Job Type:

Senior Physical Design Engineer

Job Description

Join Intel as part of the BaseBand & SoC Development group in iCDG (Intel's Communication and Devices Group). We are looking for an experienced Physical Design Engineer Leader.

In this position you will lead and contribute to the design and development of Intel's multimode cellular modem baseband 2G/3G/LTE and upcoming 5G.

  • Determines, specifies and evaluates the viability of complex hardware features and structures and ensures that software and hardware designs interface correctly.
  • Designs framework for particular functions.
  • Defines, documents and tests processes for inclusion into technical platforms, sub-system specifications, input/output and working parameters for hardware and/or software compatibility.
  • Identifies, analyzes and resolves sub-system and/or SoC design weaknesses.
  • Influences the shaping of future products by significantly contributing to the architecture used across design families.
  • Provides multi-layered technical expertise for next generation initiatives.

As a Senior Physical Design Engineer you will be part of a talented team of engineers that takes designs from RTL to complete physical implementation, in a fast-paced technically challenging environment.

Your responsibilities will include but not be limited to:

  • Strong expertise in the RTL2GDSII flow development or design implementation in leading process technologies
  • Good understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure, UPF based power methodology, etc.
  • Working experience with tools like ICC, Primetime etc used in the RTL2GDSII implementation
  • Expertise on high frequency clocking methodologies will be an added plus
  • Good automation skills in PERL, TCL, tool specific scripting on one of the industry leading Place & Route tools
  • Ability to multi-task and flexibility to work in global environment
  • Good communication skills and strong motivation for customer support
  • Strong analytical & Problem solving skills

The ideal candidate should exhibit the following traits:

  • Highly motivated technical expert with good communication and presentation skills.
  • Strong analytical ability and problem solving skills



Bachelor or Masters degree in Communication Systems, Computer Science or Electrical Engineering, PhD is a plus with 10-15 years of experience in ASIC Physical Design.

  • Requires strong knowledge and experience of custom clock and data path design.
  • Strong knowledge and experience in standard place and route flows (ICC2/Synopsys flows preferred)
  • Well versed with timing constraints, STA and timing closure (Intel flow knowledge preferred)
  • Strong knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification
  • Experience with low power design features and flows.
  • Well versed with PERL , TCL and/or any other programming knowledge.

Inside this Business Group

Intel is one of the largest suppliers of chips for the communications market. The Intel Communications group is focused on designing and building communications technologies such as Ethernet connectivity products, optical components, communications processing solutions and broadband products.

Other Locations
US, California, Santa Clara;

Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.

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