Intel invites you to join the team that develops and implements Resolution Enhancement Techniques that assist the successful pattern transfer from mask to wafer in a sub-wavelength imaging regime and enable the manufacture of every Intel silicon product. This team resides at the critical interface between Design and Manufacturing at Intel and enables the first step in silicon manufacturing. It’s operations transform the chip design to generate data for photomask fabrication and wafer inspection. This data transformation is at the cross roads of VLSI Design, Photomask Technology, Photolithography, and High Performance Computing.
What you’ll do:
As an RET Design Engineer you will perform numerical modeling, computational simulation, and correction algorithm development using scientific software applications written specifically for these purposes. You will utilize knowledge of state-of-the-art principles and theories in photolithography, optics, resists, modeling, and software engineering to investigate potential new technologies 2-4 years prior to being applied to product. This highly specialized and complex work requires the acquisition, handling, vetting and analysis of very large datasets; involves all aspects of process flow and methodology development including: requirements gathering, functional specification, scientific programming, quality assurance, technical approval, and coordination of massive distributed data processing operations.
Your Key Deliverables:
The RET Design Engineer will deliver test masks, test patterns, sampling strategies, process models, defect detection strategies, and software algorithms to perform layout correction for one or more masks at the <=10 nm technology node. New approaches, capabilities, and implementation of RET software engineering applications will also need to be defined and developed to enable Moore’s Law.
Must have Qualifications:
This position requires a Ph.D. degree in Engineering, Physical Sciences, Mathematics, Optics, Materials Science, Computer Science, or a related scientific discipline.
Familiarity with operating systems such as Linux, programming languages such as C++, scripting languages such as Perl/Python, Statistical analysis packages such as JMP and general purpose scientific applications such as MatLab is helpful.
Preference is given if your graduate work required development of skills in:
• Nanometrology (e.g. Scanning Electron Microscopy, Atomic Force Microscopy, etc.)
• Image Processing, Geometric and Fourier optics
• Design of Experiments & Analysis of Variance techniques
• Semiconductor fabrication, Lithography, Optical Proximity Correction
• Quality assurance principles and methodology such as risk management, failure analysis, statistical control, source code control and analysis, and models and standards.
The successful candidate is both detail and results oriented, relies on sound engineering judgment, and has solid data analysis, critical thinking, and presentation skills to arrive at timely solutions for complex and highly constrained problems. This opportunity is intensely collaborative & requires the continuous interaction with fellow group members and adjacent engineering teams, to absorb an in depth understanding of technology design rules, discover integrated requirements, and negotiate with internal customers to identify optimal solutions in a dynamic environment. The successful candidate will need to continue their education in this fascinating and multi-disciplinary field and expects to continuously encounter and overcome problems with root cause solutions. Does this sound like you?Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth