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Job ID: JR0032318
Job Category: Engineering
Primary Location: San Jose, CA US
Other Locations: US, California, San Jose;
Job Type:

Design Verification Engineer

Job Description


The successful candidate's minimum qualifications will include the following:

•             BS in Electrical Engineering, Computer Engineering, or equivalent with a minimum of 5+ years of experience verifying complex ASICs

•             Strong background in PCIe or Ethernet protocols

•             Experience with HW/SW debug

•             Experience with 3rd party verification IPs

•             Hands-on experience with SystemVerilog UVM

•             Knowledge of modern Testbench and Regression flows

•             Good knowledge of scripting languages

•             Attention to details, and excellent verbal and written communication skills


Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
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