Custom Physical Design Engineer
The candidate must have the ability to lead a small physical design team, chair the project meeting, and interact effectively with peers or technical leads and to meet given challenging schedule. In addition, be self-motivated with the initiative to seek constant improvements in physical design methodologies. The candidate must also possess strong troubleshoot a wide variety of possible issues in the tools, flows and design. Responsibilities will include but not be limited to: - Designs, implements, and verifies layout of reliability test structures and circuits DRC/LV/RV. Modifies physical designs to comply with latest manufacturing guidelines DFM and engineering changes ECO. Build and verify all levels of layout hierarchy leaf cell, IP block, FUB using Intel In house layout editing tool. Documents specifications and methodologies used for physical design. Attention to details and discipline in following defined methodologies. Works with engineers across different geographic zones. Train the junior physical design engineers. Creates bottomsup elements of chip design including but not limited to FET, cell, and blocklevel custom layouts, FUBlevel floor plans, abstract view generation, RC extraction and schematictolayout verification and debug using phases of physical design development including parasitic extraction, static timing, wire load models, clock generation, customer polygon editing, autoplace and route algorithms, floor planning, fullchip assembly, packaging, and verification. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. Schedules, staffs, executes and verifies complex chips development and execution of project methodologies and/or flow developments. Requires expansive knowledge and practical application of methodologies and physical design.
Inside this Business Group
- Candidate should possess a Bachelor/Masters in Electronics Engineering and with at least 8 years of working experience in custom layout design or related field.- Strong verbal and written communication skills, and able to collaborate constructively in team environment.- Proficient in all levels of layout hierarchy, and layout design methodologies.- Highly proficient with Intel layout editing tools, runsets, UNIX environment, and has strong debug skills.- Highly productive with focus on quality, and has strong schedule management skills.
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.