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Job ID: JR0004624
Job Category: Engineering
Primary Location: Santa Clara, CA US
Other Locations:
Job Type: College Grad

DFT engineer

Job Description
The position is in Intel's Design for Test Engineering Group DTEG, part of Platform Engineering Group PEG. The Candidate would be focused on delivering DFT methodology through automation for leading edge SoC microprocessor designs You will work with IP & integration design teams to understand the design and functional-mode behaviors of the logic & circuits. You will become familiar with the DFT designs of past Intel products to leverage their best-known methods and learn from their silicon experiences. Take those learnings, feed it back into the centralized dft team and deliver it to the other teams who would also benefit from the solutions. You will assist in the RTL, schematic implementation, pre-silicon validation & post silicon debug of these DFT features. Come up with innovative solution to scan coverage issues and drive methodologies & automation for it. You will be expected to deliver high-quality documentation for consumption by the pre/post-silicon teams who will use the DFT features.


Must have a MSEE degree in Computer Science, Computer Engineering, or Electrical EngineeringExperience with silicon design or validation Experience with RTL environments such as Verilog

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Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
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