Job description:As Silicon Designer you will be responsible to take part in the physical design cycle up to back-end implementation stage.Role, partition or top level back-end owner.As part of the role, you will work on the following back-end fields: -Floor-planning, clock and power distribution , place & route.-Power and noise analysis EM/IR-Drop/Xtalk.-Layout verification DRC/LVS.-Timing sign-off unit-level/top-level , interfaces.-Etc..
Inside this Business Group
-+5 years' experience in physical design of large scale designs.-In-depth understanding of static-timing analysis .-An extensive know-how in clock/power distribution and analysis, RC extraction correlation and place & route.-Experience with design practices such as multiple voltage and clock domains, integration of mixed-signal IPs and I/O integration.-Extensive experience with one of the place & route tools available today.
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.