In this position, you will be working with a team of Signal Integrity Engineers to develop the platform interconnect design guidelines for state-of-the-art server platforms, which support the latest Intel Xeon processors.Your responsibilities will include, but are not limited to: - Leading interconnect development "KIT" teams, engaging with Silicon designers, Platform designers, Package designers, AE teams, external customer design teams, etc.- Electrical modeling and simulation of high speed differential IO interconnects, such as PCIe, ENET, UPI, SATA, and USB.- Development of package and platform routing guidelines. - Definition of circuit design features required to support interconnect performance requirements. - Creation of signal measurement test plans and review of measurement results. - Correlation of measurements to simulations, and modification of models as required.
Applicants should possess a PhD in Electrical Engineering, or a MS Degree with at least 6 +years of applicable experience.
Additional desired skills and experience include:- In-depth understanding of transmission line theory and electromagnetic field concept
Experience in the design and analysis of high-speed digital interconnects, such as PCIE, DDR, ENET, SATA, USB
Experience with signal integrity simulation tools, such as HSpice, ADS, etc.
Experience with silicon device modeling methods, such as IBIS or Verilog-A
Experience with 2D and 3D field solver tools, such as XFX, iMap, HFSS, CST, etc.
Experience in PCB layout review and associated tools, such as Allegro or Mentor.
Experience with lab equipment, such as oscilloscopes, TDRs or VNAs.
Experience using scripting languages, such as Matlab, Perl or Python
Experience in the design of high-speed interconnects, such as PCIE, Fabric, etc.
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