In this position, you will be a part of a full chip team to define and implement DFT features to support post-silicon manufacturing test, debug, and characterization for IP test chips and designs. You will work with IP and integration design teams to understand the design and functional mode behaviors of the logic and circuits. You will micro-architect DFT features which are compatible with the specific product/post-silicon requirements and constraints. You will implement and verify the DFT features. You will be expected to deliver high-quality documentation describing the DFT architecture and implementation. You will work with post-silicon teams to comprehend their usage models, test time/fault coverage/data collection goals and tester capabilities and limitations.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through relevant previous school, industry jobs and/or research experience.
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.