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Job ID: JR0011137
Job Category: Engineering
Primary Location: Santa Clara, CA US
Other Locations:
Job Type: Experienced Hire

DFx Engineer

Job Description

In this position, you will be a part of a full chip team to define and implement DFT features to support post-silicon manufacturing test, debug, and characterization for IP test chips and designs. You will work with IP and integration design teams to understand the design and functional mode behaviors of the logic and circuits. You will micro-architect DFT features which are compatible with the specific product/post-silicon requirements and constraints. You will implement and verify the DFT features. You will be expected to deliver high-quality documentation describing the DFT architecture and implementation. You will work with post-silicon teams to comprehend their usage models, test time/fault coverage/data collection goals and tester capabilities and limitations.

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through relevant previous school, industry jobs and/or research experience.

Minimum Qualifications:

  • Candidate must have a Bachelors in Electrical Engineering or Computer Engineering or a Masters in Electrical Engineering or Computer Engineering with 8 years in DFT Engineering experience.
  • 5yr+ SOC engineering experience
  • Knowledge about industrial standards and practices in DFT: ATPG, JTAG, MBIST and functional tests.
  • Working knowledge of Verilog and/or VHDL and experience with simulators and waveform debugging tools Knowledge and hands on usage of industry standards DFT and design tools
  • Solid Understanding and hands on usage of design verification (DV) methodologies for pre-silicon DFT validation Experience in debugging ATPG patterns using gate level simulations, MBIST, and Verilog-based DFT verification.
  • Experience with STA constraints development, analysis for DFT modes and SDF simulations.
  • Experience in Post-Si DFT bring-up and debug.

Preferred Qualifications:

  • Knowledge of SOC development flows and methodologies.
  • 10+ Years of relevant industry experience


Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
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