The central IP team of Intel's Scalable Performance CPU Development Group SDG located at Massachusetts Microprocessor Design Center is looking for an Experienced Logic Design Engineer to contribute in the high speed IO and/or high performance power delivery/Voltage Regulator IP for Intel's client/Server/Chipset SOC designs.
You responsibilities will include but are not limited to:
The ideal candidate should exhibit behavioral traits that indicate:
The successful candidate will possess a BS, MS, or PhD degree in Electrical Engineering or Computer Engineering with 5 to 10 years of relevant industry experience in digital VLSI design.
Additional qualifications ideally include:
Low power design, understanding analog design concerns and driving to an optimal solution between analog and digital designs, familiarity with pre-silicon and post-silicon validation.
Experience in the following areas/ skills preferred:
Mixed signal design or validation, Logic design using System Verilog Micro-architecture trade-offs and documentation Low-power design using UPF and clock gating Multiple clock domain design IOSF Sideband and Chassis State machine design TAP Controller and DFX Simulation and debug experience using VCS/Verdi Customer support and debug for SOCs Synthesis and speed path debug Perl / C-shell Standard SOC Design tools and methodologies at Intel
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.