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Job ID: JR0006630
Job Category: Engineering
Primary Location: Hudson, MA US
Other Locations:
Job Type: Experienced Hire

IP Verification Engineer

Job Description

The central IP team of Intel's Scalable Performance CPU Development Group SDG located at Massachusetts Microprocessor Design Center is looking for an Experienced IP verification Engineer to contribute in the high speed IO and/or high performance power delivery/Voltage Regulator IP space for Intel's client/server/chipset SOC designs.

Responsibilities include defining the mixed signal IP verification plan, strategy and architecture, and be responsible for the development of functional validation tests to verify the IP/system meets design specification.

The responsibilities will include but not be limited to:

  • Defining, implementing, and deploying verification capabilities, methodologies, and process improvements.
  • Development and execution of test-plans, test-bench components BFMs, checkers, trackers, scoreboards and functional coverage.
  • Mixed signal behavior model development and simulation
  • Working closely with other analog, logic and verification engineers, micro-architects, and other team members to ensure quality of test-plans, verification environment, and tests.
  • Provide IP integration support to SOC customers and represent IP Verification team
  • Provide IP training and support to post silicon EV/HVM team
  • Mentorship of junior team members on verification BKMs and debug

The ideal candidate should exhibit behavioral traits that indicate:

  • Strong problem solving capability, collaborative mindset, excellent written and verbal communication skills are critical on a cross site, fast-moving team.
  • As part of a growing, dynamic IP team, the candidate must be successful working with a small team and manage multiple tasks and changing requirements, in an innovative environment.

Qualifications:

The successful candidate will possess a BS, MS, or PhD degree in in Electronic Engineering / Computer Science/Computer Engineering or related field.

At least 5 years' experience in pre-silicon ASIC/SOC verification, including but not limited to validation environment development, tests development, test plan development, tests debugging.

  • Scripting languages such as TCL/Perl or similar.
  • Hands-on experience with System Verilog coding.
  • Knowledge in SoC or large systems pre-silicon and post silicon verification.
  • Object-oriented programming knowledge C++, System Verilog Test-bench component development preferably in OVM, and test debugging skills Computer Architecture design Knowledge is required.
  • Good interpersonal communication skills.
  • Strong discipline and attention to detail in ensuring high quality verification that minimizes bug escapes to higher levels of validation


Qualifications

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
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