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Job ID: JR0008606
Job Category: Engineering
Primary Location: Santa Clara, CA US
Other Locations: Arizona, Phoenix; California, Folsom;
Job Type: Experienced Hire


Job Description
The CAE manager role will report into the IPG MIG Program and Operations office. In this position, you will be responsible for enabling and supporting any SOC team, using IO blocks from our organization. Currently, we are supporting SOC from every market segment Intel supports and all Intel business units, both on internal and external process technology. This is an opportunity to apply both technical knowledge and customer enabling skills in a team-oriented environment. Our team operates in a fluid environment enabling you to engage in a diverse set of responsibilities in support of the broad set of markets Intel supports and products Intel produces. Your responsibilities will include, but are not limited to: - Directly engaging our partners, mostly internal SOC integration teams, to provide post planning technical support to ensure Time to Market TTM production ramp - Developing collateral and supporting design integration- Replicating and debugging reported issues by identifying design issues and proposing changes - Providing technical training, consultation, and hands-on assistance to the integration teams using our IO blocks- Active participant in virtual technical teams to solve complex problems - Mentoring and guiding the broader CAE team, setting expectations and goals - Investigating, dispositioning and documenting bugs and sightings - Driving issue resolution across multiple development teams, groups and divisions


Must have- A Bachelor of Science degree in Electrical Engineering or equivalent with five or more years of relevant experience- Strong engineering background with experience in silicon IO design- Demonstrated leadership ability - Excellent analytical and problem solving skills- Ability to apply critical thinking - Tolerance of ambiguity - Proven verbal and written communication skills, proficient technical writing/presentation skills- Ability to work with minimal supervision, establish-track quarterly objectives, multitask effectively - Ability and willingness to travel domestically and internationally Nice to have - Customer-facing experience- Experience in design debug, specifically active participation in full chip integration and platform power-on

Inside this Business Group

Other Locations

Arizona, Phoenix; California, Folsom;

Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.

Position of Trust. This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Talent Consultant.

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