Inside this Business Group
The ideal candidate should have 10+ years of experience in high-speed serial links. Very knowledgeable about the common high-speed serial data protocols NRZ/PAM4 and system standards CAUI-4 in wireline Communications.Deep knowledge of analog CMOS/BiCMOS designs in 180nm, 90nm, 45nm and 28nm. Experience with high speed mixed signal circuits e.g., serializer, deserializer, counters, dividers, etc.. Experience with Analog RF front end circuits such as Drivers, Trans-Impedance Amplifiers TIA, Limiting Amplifiers, for optical transceivers, etc. Experience in analyzing link budget for high-speed serial linksGood understanding of different CDR architectures. Prior experience in implementing CDR Good knowledge of TX/RX equalization techniques.Experience in Matlab/ADS/IBIS-AMI system modeling of SERDES circuits.Static timing analysis tools. Able to create block-level requirements from link budget analysis and modelsGood experience in lab testing of high-speed serial links and defining equipment needsAble to create Verilog-A/AMS behavioral models in Cadence.