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Job ID: JR0009069
Job Category: Intern/Student
Primary Location: Haifa, IL
Other Locations:
Job Type: Intern

Physical Designer Student

Job Description
Role including Layout synthesis editing ICC synopsis Floor plan and verification of VLSI circuits and Design Rules checkers. Target is to convergence with correlation to extraction results and process constrains.Position will take place in Haifa for out Layout team.


Qualifications: 1. high self-learning abilities2. Strong interpersonal Skills3. Demonstrated ability to work effectively within a team environment4. Excellent written communication skills in English

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

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