Come and join us! Intel is seeking highly qualified candidates to join our Data Center Group (DCG) team as a Senior Design Lead! You are joining an innovative team in San Jose in which responsible for developing an advance ASSP that helps to drive our Data Center Group road map. Our organization works on all levels of ASIC development, spanning high-level architecture to RTL design and verification and volume manufacturing. We are looking for a motivated and astute individual to join our team to contribute to our success.
As a Senior Design Lead you will oversee definition, design, verification, and documentation for a key functional block of a complex ASSP. As such, you will determine architecture design, logic design, and system simulation as well as define module interfaces/formats for simulation. You will perform Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs. Other responsibilities include contributing to the development of multidimensional designs involving the layout of complex integrated circuits and performing all aspects of the SoC design flow from high-level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. You will also analyze equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. You may also review vendor capability to support development.
Additional responsibilities and skills/experience needed for this role include:
- Written uArch specification based on the functional requirement of Feature / Performance / Scale information. The detail uArch spec includes actual interface protocol, interface timing diagram, pipeline detail, state-machine.
- Write the actual RTL in System Verilog that can be synthesized efficiently that will meet our timing, area, and power constraint.
- Develop or Review Test Plan of the functional block. The Test Plan should be clear about corner case and detail functional coverage requirement.
In this position you will gain invaluable experience which will allow growth and expanded opportunities within this business group as well as future possible opportunities with other business groups within Intel.
The Data Center Group (DCG) drives new products technologies from high-end co-processors for supercomputers to low-energy systems for enterprise and the cloud, as well as solutions for big data and intelligent devices. The group is a worldwide organization that develops the products and technologies that power nine of every 10 servers sold worldwide.
Inside this Business Group
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Required Qualifications:
Bachelor Degree in Computer Science, Electrical Engineering, or related discipline with 4+ years of work experience, Masters in Computer Science, Electrical Engineering, or related discipline with 3+ years of work experience, or a PhD in Computer Science, Electrical Engineering, or related discipline.
- 4+ years of experience in high performance pipeline design.
- 4+ years of experience and familiarity in standard specification technology (ie PCIe, SR-IOV, VirtIO, NVMe).
- 3+ years of experience in low-power design in both uArch technique, and actual implementation (Clock Gating, Voltage Scaling, Voltage Island).
- 3+ years of experience and familiarity with TCP_IP OffLoad Engine (ie TSO, RSS).
- 3+ years of proficiency in scripting language (Perf, Phython, make file, etc.).
Additional Preferred Qualifications:
- Familiar in standard specification technology like (PCIe, SR-IOV, VirtIO, NVMe).
- Familiar with TCP_IP OffLoad Engine (such as TSO, RSS).
- Experience in low-power design in both uArch technique, and actual implementation (Clock Gating, Voltage Scaling, Voltage Island).
- Basic Knowledge of OVM/UVM methodology.
- Proficient of System Verilog Functional Coverage assertion development.
- Proficient in Synopsys , Cadence tool set on synthesized script, STA script.
- Experience in Java, C, C++ and logical design a plus.
- Excellent written and verbal communication skills.