Inside this Business Group
Intel Data Center Group DCG/Connectivity Group CG - Silicon Photonics Product Division SPPD is looking for a senior packaging engineer in next generation optical module development team. The job responsibility includes: Developing state of the art Silicon Photonics SiPh device packaging and assemblies. Survey, assess and select packaging/assembly architectures for silicon-photonic System In Package SIP solutions.
Define and develop test vehicles to demonstrate and debug the design rules, the package designs, the subcomponent integration steps and the process flows. Validate the design rules at both the silicon electronic and active optical and the package assembly levels. Working with mechanical, electrical, optical, & test engineers to determine process requirements and define process capabilities. Leading hands-on development of wafer bumping, die prep, die attach and assembly processes using micron level pick and place machines for next-generation transceiver products. Leading system-in-package fan-out wafer level device integration through design, process and reliability risk assessment, risk mitigation and developing DOE to provide technical problem solving by model based.. Developing technical expertise on micron level pick/place and alignment machines Performing characterization and failure analysis on next-generation SiPh devices and assemblies Development of automated optical alignment equipment and processes for Silicon Photonics devices Interacting with and travelling to OSATs and CMs to transfer processes and equipment to a production line. Travelling to vendors for equipment evaluation and buy-off. Leading reviews of process development activities
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Must have a BS, MS or PhD in Mechanical, Electrical or Chemical Engineering, Materials Science or similar technical discipline
Minimum 8+ years of experience with packaging development and/or assembly process development including chip-package interactions and qualification
Minimum 3+ years of experience with silicon CMOS backend fabrication processes including litho, plating, CVE/PVD, etch, thin-film technologies
Minimum 5 years of experience with wafer bumping Lead Free, Cu pillar, redistribution layer and flip chip CSP/BA package processes
In depth understanding of assembly processes such as wafer thinning, dicing, die bonding, wire bonding, flip chip assembly/underfilling, etc. Optical alignment and assembly is plus.
Excellent verbal and written communication, interpersonal skill.
Detail oriented problem solver, sense of urgency and commitment to achieve targeted goals.
Ability to work independently with limited direction, as well as in a team environment across functional and organizational boundaries is required.
Demonstrated ability to juggle multiple priorities and deliver against a schedule
Educational research focus in microelectronic or micro-photonic packaging/assembly Industrial experience with fan-out wafer level integration, Through Silicon Vias TSVs and 2.5D/3D system integration
Prior work experience with IC packaging processes including WLCSP, flip chip bumping, grinding/dicing Experience in SiPh assembly processes and design rulesProficiency in JMP or statistical analysis tool
Team player with good communication skills.
Strong technical leadership skills.
Proven experience in executing complex projects that require cross-functional teamwork