Come and join us! Intel is seeking highly qualified candidates to join our Data Center Group (DCG) team as a Senior Designer! You are joining an innovative team in San Jose in which responsible for developing an advance ASSP that helps to drive our Data Center Group road map. Our organization works on all levels of ASIC development, spanning high-level architecture to RTL design and verification and volume manufacturing. We are looking for a motivated and astute individual to join our team to contribute to our success.
As a Senior Designer you will be responsible for the design and development of electronic components. This includes the design of chip layout circuit design, circuit checking, device evaluation and characterization, documentation of specifications, prototype construction and checkout. Additionally you will be responsible for the modification and evaluation of semiconductor devices and components, performing developmental and/or test work, reviewing product requirements and logic diagrams, and planning and organizing design projects or phases of design projects. You will also respond to customer/client requests or events as they occur and will develop solutions to problems utilizing formal education and judgement.
Additional responsibilities and skills/experience needed for this role include:
- Written uArch specification based on the functional requirement of Feature / Performance / Scale information. The detail uArch spec includes actual interface protocol, interface timing diagram, pipeline detail, state-machine.
- Write the actual RTL in System Verilog that can be synthesized efficiently that will meet our timing, area, and power constraint.
- Develop or Review Test Plan of the functional block. The Test Plan should be clear about corner case and detail functional coverage requirement.
In this position you will gain invaluable experience which will allow growth and expanded opportunities within this business group as well as future possible opportunities with other business groups within Intel.
The Data Center Group (DCG) drives new products technologies from high-end co-processors for supercomputers to low-energy systems for enterprise and the cloud, as well as solutions for big data and intelligent devices. The group is a worldwide organization that develops the products and technologies that power nine of every 10 servers sold worldwide.
Inside this Business Group
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Required Qualifications:
Bachelor Degree in Computer Science, Electrical Engineering, or related discipline with 4+ years of work experience, Masters in Computer Science, Electrical Engineering, or related discipline with 3+ years of work experience, or a PhD in Computer Science, Electrical Engineering, or related discipline.
- 4+ years of experience in high performance ASSP logical design.
- 4+ years of experience and proficiency in Verilog or System Verilog.
- 3+ years of experience and understanding of scripting language (Perf, Phython, make file, etc).
- 3+ years of experience with the ability to develop synthesis script for Synopsys / Cadence too set
- 3+ years of experience developing static timing analysis script.
Additional Preferred Qualifications:
- Familiar in standard specification technology like (PCIe, SR-IOV, VirtIO, NVMe).
- Familiar with TCP_IP OffLoad Engine (such as TSO, RSS).
- Experience in low-power design in both uArch technique, and actual implementation (Clock Gating, Voltage Scaling, and Voltage Island).
- Experience in Java, C, C++ and logical design a plus.
- Excellent written and verbal communication skills.