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Job ID: JR0007911
Job Category: Engineering
Primary Location: San Jose, CA US
Other Locations:
Job Type: Experienced Hire

DFX Senior Designer

Job Description

Come and join us! Intel is seeking highly qualified candidates to join our Data Center Group (DCG) team as a DFX Senior Designer!  You are joining an innovative team in San Jose in which responsible for developing an advance ASSP that helps to drive our Data Center Group road map.  Our organization works on all levels of ASIC development, spanning high-level architecture to RTL design and verification and volume manufacturing. We are looking for a motivated and astute individual to join our team to contribute to our success.

As a DFX Senior Designer you will be a senior uArch/designer for Test/Debug/Manufacturability/Reliability. You will be a part of a full-chip team to define and implement DFT features to support post-silicon manufacturing test, debug, and characterization for IP test chips and designs. You will closely work with IP and integration design teams to understand the design and functional mode behaviors of the logic and circuits. You will micro-architect DFT features which are compatible with the specific product/post-silicon requirements and constraints. You will implement and verify the DFT features. You will be expected to deliver high-quality documentation describing the DFT architecture and implementation. You will work with post-silicon teams including Electrical Validation to comprehend their usage models, test time/fault coverage/data collection goals and tester capabilities and limitations.

Additional responsibilities and skills/experience needed for this role include:

- Strong communication skills set to work with IP developer, product engineer to drive definition and actual DFT implementation to assure a high yield, low defect product for high volume manufacturing.

- Strong technical hand-on experience on at-speed JTAG, Scan, LogicBist, MBist tool set.

- Experience in high speed IO testing (DDR4 PHY).

- Experience in high speed serdes testing.

In this position you will gain invaluable experience which will allow growth and expanded opportunities within this business group as well as future possible opportunities with other business groups within Intel.

The Data Center Group (DCG) drives new products technologies from high-end co-processors for supercomputers to low-energy systems for enterprise and the cloud, as well as solutions for big data and intelligent devices. The group is a worldwide organization that develops the products and technologies that power nine of every 10 servers sold worldwide.


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Required Qualifications:
Bachelor Degree in Electrical Engineering or related discipline with 6+ years of work experience, Masters in Electrical Engineering or related discipline with 4+ years of work experience, or a PhD in Electrical Engineering or related discipline with 2+ years of work experience.
- 6+ years of experience in DFT, DFM role.
- 6+ years of experience and understanding of the complete IC development process from specification to high volume manufacturing.
- 4+ years of experience and knowledge of COT flow, with high speed internal memory, high speed Serdes, and other high speed IO for DFT, and DFM requirements.

Additional Preferred Qualifications:
- Experience in high speed IO testing (DDR4 PHY) will be a plus.
- Experience in high speed serdes testing will be a plus.
- Experience in Java, C, C++ and logical design a plus.
- Excellent written and verbal communication skills.

Inside this Business Group


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
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