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Job ID: JR0006671
Job Category: Engineering
Primary Location: Bangalore, KA IN
Other Locations:
Job Type: College Grad

GPU Performance Modelling Engineer

Job Description
Intel's Visual and Parallel computing group is looking for candidates to join the Simulator development team to work on building a performance/ functional simulator for Next-Gen Graphics the largest IP in any intel SOC. This simulator is a critical tool for architecture exploration and providing a reference model for validation of the GPU. In this position, you will be responsible for design, coding, validation including performance co-relation and maintenance of units/ cluster level models in the GPU pipeline. The job will involve intense engagement with IP architects, RTL design and Driver team to bring-up the performance model and deploy this into production for both internal and external customers. This position offers a unique opportunity to impact emerging GPU application areas such as Augmented / Virtual reality, Deep Learning, Computer Vision, GPU Virtualization and Media Servers.You responsibilities will include but not limited to :* Developing functional/performance model of the graphics hardware in C++ or System C. * Working with Architecture/ Microarchitecture teams in performing studies on current and future generation of GPUs.* Enabling graphics driver and external OEMs to use this model* Developing test plans, test writing and validating the reference models.* Working with the architecture, design and software teams for debugging issues and resolving them


Qualifications:You must possess a Master's or PhD degree in Computer Science / ECE. Additional qualifications include: * Strong programming experience in C/C++ or System C and familiar with scripting languages.* Strong Computer Architecture knowledge* Prior experience in Simulator development is a plus* 3D Graphics knowledge is desirable.* Strong analytical and problem solving skills. Ability to multitask.* Strong written and verbal communication skills.* Ability to work in dynamic and team oriented environment.* Familiarity with ASIC design flow, validation concepts, coverage, etc. is desirable.

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