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Job ID: JR0007917
Job Category: Engineering
Primary Location: San Jose, CA US
Other Locations:
Job Type: Experienced Hire

Senior Pre Silicon Verification Lead

Job Description

Come and join us! Intel is seeking highly qualified candidates to join our Data Center Group (DCG) team as a Senior Pre-Silicon Design Verification Lead!  You are joining an innovative team in San Jose in which responsible for developing an advance ASSP that helps to drive our Data Center Group road map.  Our organization works on all levels of ASIC development, spanning high-level architecture to RTL design and verification and volume manufacturing. We are looking for a motivated and astute individual to join our team to contribute to our success.

As a Senior Pre-Silicon Design Verification Lead, you will develop pre-Silicon functional validation tests to verify systems will meet design requirements. You will create test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests. You will also analyze and use results to modify testing.

Responsibilities will include but are not limited to:

1. Work as senior DV Lead for the DUT IP verification team and be responsible for developing an efficient and effective constraint random environment using OVM/UVM base DV infra-structure. 

2. Write the uArch specification of the OVM/UVM testbench base on the Arch/uArch definition of DUT.

3. Develop the actual OVM/UVM DV Agent (Monitor, Driver, ScoreBoard).

4. Collecting and Closing on all functional coverage analysis and enhance the test case to cover the coverage gap.

5. Review the uArch/implementation of DV TB / Agent development. Provide feedback and enhancement for improvement of simulation efficiency, and ease of enhancement.

6. Work with the actual SW/Firmware team of how the DUT is being use so as to develop the Test Case Sequence mimic the actual SW usage.

In this position you will gain invaluable experience which will allow growth and expanded opportunities within this business group as well as future possible opportunities with other business groups within Intel.

The Data Center Group (DCG) drives new products technologies from high-end co-processors for supercomputers to low-energy systems for enterprise and the cloud, as well as solutions for big data and intelligent devices. The group is a worldwide organization that develops the products and technologies that power nine of every 10 servers sold worldwide.


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Required Qualifications:
Bachelor Degree in Computer Science, Electrical Engineering, or related discipline with 6+ years of work experience, Masters in Computer Science, Electrical Engineering, or related discipline with 4+ years of work experience, or PhD in Computer Science, Electrical Engineering, or related discipline with 2+ years of work experience.
- 6+ years of experience in VMM/OVM/UVM in verification lead.
- 4+ years of experience in high performance ASSP design.
- 4+ years of proficiency in OVM/UVM/SystemVerilog.
- 3+ years of experience in VCS and Coverage.
- 3+ years of experience in understanding of scripting language (Perf, Phython, make file, etc.).

Additional Preferred Qualifications:
- Master’s Degree or higher is preferred.
- 2+ years of experience leading a small DV team to achieve a challenging DV goal.
- Experience in Java, C, C++ and logical design is a plus.
- Familiar in standard specification technology like (PCIe, SR-IOV, VirtIO, NVMe).
- Familiar with TCP_IP OffLoad Engine (such as TSO, RSS).

Inside this Business Group


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
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