Come and join us! Intel is seeking highly qualified candidates to join our Data Center Group (DCG) team as a Senior Pre-Silicon Design Verification Engineer! You are joining an innovative team in San Jose in which responsible for developing an advance ASSP that helps to drive our Data Center Group road map. Our organization works on all levels of ASIC development, spanning high-level architecture to RTL design and verification and volume manufacturing. We are looking for a motivated and astute individual to join our team to contribute to our success.
As a Senior Pre-Silicon Design Verification Engineer, you will develop pre-Silicon functional validation tests to verify systems will meet design requirements. You will create test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests. You will also analyze and use results to modify testing.
Responsibilities will include but are not limited to:
1. Develop the actual OVM/UVM DV Agent (Monitor, Driver, ScoreBoard).
2. Develop the actual DV test.
3. Collecting and Closing on all functional coverage analysis and enhance the test case to cover the coverage gap.
4. Develop the actual micro-controller test in actual C / C++ / Asembly using the micro-controller SDK
5. Ability to use Tensilica SDK to develop Tensilica binary code for testing
In this position you will gain invaluable experience which will allow growth and expanded opportunities within this business group as well as future possible opportunities with other business groups within Intel.
The Data Center Group (DCG) drives new products technologies from high-end co-processors for supercomputers to low-energy systems for enterprise and the cloud, as well as solutions for big data and intelligent devices. The group is a worldwide organization that develops the products and technologies that power nine of every 10 servers sold worldwide.
Inside this Business Group
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Required Qualifications:
Bachelor Degree in Computer Science, Electrical Engineering, or related discipline with 4+ years of work experience, Masters in Computer Science, Electrical Engineering, or related discipline with 3+ years of work experience, or PhD in Computer Science, Electrical Engineering, or related discipline.
- 4+ years of experience in high performance ASSP design.
- 4+ years of experience in VMM/OVM/UVM in verification.
- 3+ years of proficiency in OVM/UVM/SystemVerilog.
- 3+ years of proficiency in C / C++ / Assembly language.
- 3+ years of experience in VCS and Coverage.
- 3+ years of experience with understanding of scripting language (Perf, Phython, make file, etc).
Additional Preferred Qualifications:
- Master’s Degree or higher is preferred.
- 2+ years of experience leading a small DV team to achieve a challenging DV goal.
- Experience in Cadence Tensilica is a plus.