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Job ID: JR0007030
Job Category: Engineering
Primary Location: Folsom, CA US
Other Locations:
Job Type: Experienced Hire

Component Design Engineer

Job Description

At the heart of Intel IP development, we are an RTL Design team working in High Speed IO Protocols designing advanced Protocol Exercisers. 

Component Design Engineers are responsible for the design and development of electronic components.

Responsibilities may include:

  • The design of chip layout circuit design, circuit checking, device evaluation and characterization,
  • Documentation of specifications, prototype construction and checkout,
  • Modification and evaluation of semiconductor devices and components,
  • Performing developmental and/or test work,
  • Reviewing product requirements and logic diagrams,
  • Planning and organizing design projects or phases of design projects.
  • Responds to customer/client requests or events as they occur.
  • Develops solutions to problems utilizing formal education and judgment.
  • Responsible to use Verilog to design RTL for FPGA related to HSIO.

Minimum Qualifications:

BSEE or MSEE or similar technical BS or MS degree plus at least 8 years of experience in a field relevant to this job.

Responsibilities include:

  • RTL Design for FPGA
  • Synthesis of RTL Design for FPGA
  • FPGA Floorplanning

Preferred Skills:

In addition to the Minimum Requirements listed above, strong experiences with Verilog, System Verilog and Python.


Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
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