In this position, candidate will be responsible for physical design implementation of partitions/blocks/Hard Macros.
This includes, interacting with RTL/Design team to define right synthesis recipe, cleanup logic equivalence checks, Block level floor-planning, Place & Route, CTS, Timing convergence/STA activities, LVS & DRC cleanup, Electrical Rule Fixes and Quality fixes.
You will also be responsible to drive the methodology development in critical design issues, troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention.
In addition, be self-motivated with the initiative to seek constant improvements in the physical design methodologies.
The candidate must also possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment
Inside this Business Group
Bachelors or Masters in Electrical Engineering or equivalent with 4+ years of experience in physical design. Candidate should have the hands on experience of floorplanning, Synthesis, PNR flows. STA convergence and RV/IR convergence, Deep Domain expertise in any of backend signoff activities is an additional plus. *Effective presentation and communication * Strong problem solving skills and an ability to think outside the box * Ability to work / lead effectively in cross functional teams
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.