In this position, you will be a validation manager in the pre-silicon IP validation team in Intel's Scalable Performance CPU Development Group (SDG). You will be responsible for validating the CPU coherency fabric design IP for high-end, server-oriented computing products.
Plans, provides resources for and directs activities in engineering function to meet schedules, standards, and cost.
Cultivates and reinforces appropriate group values, norms and behaviors.
Identifies and analyzes problems, plans, tasks, and solutions.
Provides guidance on employee development, performance, and productivity issues.
Plans and schedules daily tasks, uses judgement on a variety of problems requiring deviation from standard practices.
Inadequacies and erroneous decisions would cause moderate inconvenience and expense.
The microprocessor has driven the digital revolution, dramatically transforming the way we live, work, and play. As a coherency fabric IP validation manager, you will have an integral role in leading a technical team designing and delivering innovative coherent fabric architectures with rich feature sets to deliver higher levels of performance, energy-efficiency and value that form the computing backbone of the connected world.
Your responsibilities will include but not be limited to:
First line management of engineers
Setting goals, schedule and staging plans along with tracking and enabling execution for team
Technical hands-on contributions
Contributing to organizations longer-term technical visions
Team's deliverables include:
Validation of server features in cluster test environments
Validating designs by authoring validation plans, writing focus tests, creating templates defining coverage strategies, developing and analyzing coverage monitors, creating event injectors, writing architectural and micro-architectural correctness checkers, developing BFMs (Bus Functional Model), running functional simulations, and debugging failures to root cause
Maintaining and enhancing the validation infrastructure by creating new tools to support validation.
The ideal candidate will be able to demonstrate the following behaviors:
Strong leadership skills and drive to guide and motivate team
Strong communication skills and ability to influence and work across large teams
BS or MS in EE, CS, or Computer Engineering
10+ years of hands-on experience & track-record of success in pre-silicon validation
4 years technical leadership / management experience
3 years of experience of SV OVM/UVM
3 years of experience computer architecture
3 years of experience of validation architecture and infrastructure
3 years of experience of stat of the art coherency protocols and interconnect protocols
Candidates should also have experience with RTL simulators, VCS preferred
Experience specifying and developing test bench components, specifying and developing, and and strong debug capabilities, and experience specifying, implementing and analyzing functional coverage.
Experience with validation frameworks such as OVM/UVM desired.
Good interpersonal skills and the ability to work in a highly cooperative team environment across several time zones are also desirable.
In this role you will be part of the Scalable Performance CPU Development Group (SDG) design team, working on next-generation server product SOCs and IPs.
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.