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Job ID: JR0005040
Job Category: Engineering
Primary Location: Folsom, CA US
Other Locations:
Job Type: Intern

IP Logic Verification Engineer

Job Description
Develops preSilicon functional validation tests to verify system will meet design requirements. Creates test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests. Analyzes and uses results to modify testing.


Deep experience in logic design and RTL verification Strong background in RTL level Digital IC Design using System Verilog and/or Verilog Experience with languages and standards such as Verilog, System Verilog, Perl, Shell scripting, UPF.Strong ASIC and/or SoC design experience.System Verilog verification methodology OVM/UVM, RTL design quality checking lint, low power QA, cross-clock domain checks -experience in high speed interconnects like Memory/ imaging or logic subsystem design and controller design is a huge plusMasters level System Verilog/VHDL Proven, hands-on knowledge of System Verilog, OVM and object-oriented verification concepts * Strong experience with architecting verification environments and components, random traffic generators, coverage-based validation and debug * Working knowledge of standard bus protocols like PCI, AHB, etc., strong understanding of logic design and computer architecture fundamentals * Experience with SIP/SoC standard tools and methodologies Saola, ACE, VCS, etc., C/C++ & Perl scripting. * Experience in defining, implementing and deploying verification capabilities and methodologies. * Must demonstrate strong initiative, teamwork, planning, and communication abilities as he/she will be driving verification capabilities and requirements impacting multiple projects. * Excellent verbal and written communications skills as well as ability to be results oriented in a team environment.

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