Come and join us! Intel is seeking highly qualified candidates to join our Data Center Group (DCG) team as a Pre-Silicon Verification Engineer!
As a Pre-Silicon Verification Engineer you will create verification test plans, develop the architecture and design of the verification environment in OVM/UVM, and develop/run/debug tests and functional coverage in SystemVerilog. You will also mentor other engineers in using the verification infrastructure and creating test benches as well as develop and maintain long term design verification strategy.
In this position you will gain invaluable experience which will allow growth and expanded opportunities within this business group as well as future possible opportunities with other business groups within Intel.
The Data Center Group (DCG) drives new products technologies from high-end co-processors for supercomputers to low-energy systems for enterprise and the cloud, as well as solutions for big data and intelligent devices. The group is a worldwide organization that develops the products and technologies that power nine of every 10 servers sold worldwide.
Inside this Business Group
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Required Qualifications:
Bachelor degree in Computer Science, Electrical Engineering, or equivalent with 6+ years of industry experience or a Master's degree in Computer Science, Electrical Engineering, or equivalent with 4+ years of industry experience.
- 6 plus years of hands-on verification experience using SystemVerilog and OVM/UVM to include having built a test environment based on OVM/UVM.
- 6 plus years of proven track record in ASIC verification from environment development to tests development.
- 4 plus years of experience in development and deployment of verification strategies and methodologies across teams and organizations.
- 4 plus years of expert level knowledge of simulation tools such as VCS from Synopsys.
Additional Preferred Qualifications:
- Master's degree or higher preferred.
- 10 plus years of hands-on verification experience using SystemVerilog and OVM/UVM is highly preferred.
- 4 plus years of experience with leading a team of 5 or more engineers to include mentoring junior engineers highly preferred.
- Experience with creation of plans, schedules and cost estimates for design verification efforts desired.
- Strong understanding of engineering design principles preferred.
- Experience in C/C++ is highly desirable.
- Experience in network ASIC design verification is a plus, such as Ethernet, PCI-Express, InfiniBand, SONET.
- Proficiency in scripting languages and utilities including Make, Perl, Python, etc.
- Excellent written and verbal communication skills.
Texas, Austin; Wisconsin, Eau Claire;