Creates emulation/Field Programmable Gate Array FPGA models from a Register Transfer Level RTL design using emulation/FPGA synthesis, partitioning and routing tools. Defines and documents RTL changes required for emulation/FPGA. Develops hardware and software collaterals and integrates it with the emulation/FPGA model. Tests and debugs the emulation/FPGA model and collaterals. Defines and develops new capabilities & HW/SW tools to enable acceleration of RTL and improve emulation/FPGA model usability for preSilicon and postSilicon functional validation as well as SW development/validation. Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform. Interfaces with and provides guidance to presilicon Validation teams for optimizing preSi validation environments, test suites and methodologies for emulation efficiency. Develops and applies automation aids, flows and scripts in support of emulation easeofuse and improvement of equipment utilization.
Inside this Business Group
The candidate must possess a Bachelor or Master of Science in Computer Engineering or Computer Science or Electrical Engineering with 3+ years of relevant experience.Additional qualifications include:- Strong background of computer architecture, logic verification with a good understanding of logic design concepts.- Good working knowledge of Verilog, System Verilog.- Strong software programming skills, proficient in C and/or C++, familiar with Linux*/UNIX* based development environments, tools, and script languages such as Perl, Python, and good software engineering practices - Excellent problem-solving skills and a self starter- Good communication and project management skills- Ability to work effectively in a cross-site team environment
Oregon, Hillsboro; California, Santa Clara;