Oversees definition, design, verification, and documentation for SoC (System on a Chip) development.
Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation.
Performs Logic design for integration of cell libraries, functional units and sub-systems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits.
Performs all aspects of the SoC design flow from high-level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing.
Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results.
May also review vendor capability to support development.
In this position, you will be working alongside a World-class SOC design team within the Scalable Performance CPU Development Group (SDG) delivering next-generation Xeon products and related IPs for Server markets.
Educational requirements for this position are a BSEE/CE minimum, MS preferred.
Also required are 6-8 years of experience in ASIC logic verification and strong software skills.
Experience using 1 or more of the following languages: System Verilog/Verilog, Perl, C/C++.
Strong background in computer architecture.
Familiarity with hardware description languages.
Candidates should also have experience with RTL simulators, VCS preferred.
Experience specifying and developing test bench components, specifying and developing, and strong debug capabilities, and experience specifying, implementing and analyzing functional coverage
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.