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Job ID: JR0815069
Job Category: Engineering
Primary Location: Haifa, IL
Other Locations:
Job Type: Experienced Hire

Pre-silicon production reset validation (MIG MVE)

Job Description

Intel's MVE - MIG - HTD is looking for motivated engineers to join the team to work in the highly challenging environment of product development across Intel's product families.

HTD is specifically responsible for paving the way for test content development and spearheading product test enabling for product engineers worldwide. Responsibilities of the engineers may include:

Silicon ready HVM reset sequences end to end ownership (Arch' definition -> Silicon)

Pre-Silicon development and validation of reset sequences and functional tests capabilities

Support DFT Design and Architectural Validation teams

Silicon debug to identify functional and DFT related bugs

Creating an infrastructure for test content development using advanced simulation and emulation tools.


BSc in Computer Engineering, Electrical Engineering or computer science .
Skills and experience-
Must: Pre and/ or Post Silicon validation/verification/debug , Pre – simulation/emulation
Post – testers / content generation , Experience in working with IA/ARM Architectures (either IP or Full Chip level) , Python/Perl (or any other script language) , High communication skills & team player- Problem solver, Costumers orientation , Independent.
Advantage / Nice to have:
DFT (design for testerability) / DFD (design for debug)
Pre/Post Silicon Reset sequences
Emulation / FPGA

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

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