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Job ID: JR0003385
Job Category: Engineering
Primary Location: Eau Claire, WI US
Other Locations: Oregon, Hillsboro;
Job Type: Experienced Hire

SOC Logic Design Engineer

Job Description

Design high speed link PCS and PHY.  Performs logic design, Register Transfer Level RTL coding, and simulation to generate cell libraries, functional units, and subsystems for inclusion in full chip designs. Participates in the development of Architecture and Microarchitecture specifications for the Logic components. Provides IP integration support to SoC customers and represents RTL team.

Minimum Qualifications:

BSEE with at least 4+ years of experience or MSEE with 3+ years of experience

Expertise in high-speed Link design, RTL design and validation


Qualifications

Inside this Business Group

TBD



Other Locations

Oregon, Hillsboro;


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.

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