Design high speed link PCS and PHY. Performs logic design, Register Transfer Level RTL coding, and simulation to generate cell libraries, functional units, and subsystems for inclusion in full chip designs. Participates in the development of Architecture and Microarchitecture specifications for the Logic components. Provides IP integration support to SoC customers and represents RTL team.
BSEE with at least 4+ years of experience or MSEE with 3+ years of experience
Expertise in high-speed Link design, RTL design and validation
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