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The ideal candidate should exhibit the following behavioral traits: Strong problem-solving skills to find solutions to IO problems quickly and accurately.Independently work across Validation disciplines and geographies. Ability to multitask and work in a dynamic and team oriented environment.Strong written and verbal communication skillsQualifications:You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are considered a plus factor in identifying top candidates.Must have a MS or PhD in Electrical Engineering or Computer Engineering.Minimum 5 year experience in mixed signal design & validation, RTL design and/or scripting in Pre or Post Si environment.Minimum 3 year experience with software development, demonstrated proficiency with Python, C/C++.Experience with hardware lab with test equipment, computer systems, and/or test stations is a plus.Strong debug and data analysis skills experience in defining experiments for technical teams. Good Knowledge of Memory IO technologies i.e. DDR3/4, LPDDR3/4, U/R/LR DIMM JEDEC standards & DFX is a plus. Knowledge in system interconnect signal integrity and electrical validation fundamentals
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.