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Job ID: JR0003746
Job Category: Engineering
Primary Location: Hudson, MA US
Other Locations:
Job Type: Experienced Hire

Silicon Architect

Job Description

You will be part of a team doing research for an HPC architectural study exploring innovation in system architecture to achieve performance across a broad scope of system components including computing core/uncore, networking on-die, on-MCP, off-MCP, silicon technologies, packaging, reliability and system software. The team evaluates technology tradeoffs for performance objectives. Technical topics to be investigated include exploring fabric protocol options, exploring physical and link technology options including optical interconnect technology, characterizing latency and bandwidth capability for each option, exploring fabric routing options, exploring costs associated with fabric options, and exploring paths available to reuse Intel commercially developed fabrics.


Qualifications

The desired candidate will have a BS in Electrical Engineering or Computer Science or related field with at least 6 years of experience or MS with 4 years of experience or a PhD or equivalent. A minimum of 6 years of experience with on-package interconnect is required. A minimum of 6 years of experience with module and rack level interconnect is required. Preferred skills include experience with large-scale HPC systems, high performance interconnect technology such as Omni-Path, InfiniBand and iWARPStrong and an advanced understanding of software and hardware interaction. Benchmarking and technology evaluations of new or emerging memory hierarchy, file and storage systems and network technologies is also required.

Inside this Business Group

TBD


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
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