You will be part of a team doing advanced pathfinding for an HPC architectural study exploring innovation in system architecture to achieve performance across a broad scope of system components including computing (core/uncore), networking (on-die, on-MCP, off-MCP), silicon technologies, packaging, reliability and system software. The team evaluates technology tradeoffs for performance objectives.
For this exciting senior technical role working both with world-class technology leaders within Intel as well as interface with government customers of Intel Federal to deliver architectural solutions that address real-world high performance computing challenges for the Federal government. We are looking for a candidates who thrive in a results-driven environment working with cross-discipline teams.
In this role you will be challenged to research, define, architect and evaluate solutions for on-die interconnect fabrics with a focus on current and next generation technologies/topologies. Analysis of on-die interconnect requirements such as coherence, transaction order, power and clocking schemes, packet definition, virtual channels, dependence & deadlock analysis, redundancy.
Focus may also include: memory size and organization options across the memory hierarchy; memory interconnect fabric structure options across the memory hierarchy; memory latencies across the memory hierarchy; processing element (PE, i.e., blocks containing ALUs) memory bandwidth and overall die bisectional bandwidth capability; architectures for connecting PEs to the memory hierarchy; off-chip memory architecture and technology options.
Will need to collaborate with power and performance modeling teams to define, model, and evaluate architectural features and associated performance/area/power tradeoffs.
Must have a BS in Electrical Engineering or Computer Science or related field with at least 6 years of experience or MS with 4 years of experience or a PhD or equivalent
Minimum of 6 years of experience with on-die interconnect Minimum of 6 years of experience with on-die memory hierarchies
Preferred Skills: Experience with large-scale HPC systems, benchmarking and technology evaluations of new or emerging memory hierarchy, file and storage systems, and network technologies. Understanding of microprocessor architecture concepts including cache architecture, system-level coherency, shared virtual memory, network-on-chip and related protocols. Comfortable with working on/developing performance simulation models.
This position is within Intel Federal LLC. Intel Federal LLC is a wholly-owned Intel subsidiary that manages contracts with the U.S. Government (USG). This position involves work on U.S. Government contracts, which may impose certain security requirements. If you are a U.S. citizen, the government may require that you certify that you are a U.S. citizen. If you are not a U.S. citizen, the government may require you to pass a security check before you can be approved to work on the project.
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.