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Job ID: JR0811672
Job Category: Engineering Management
Primary Location: Hudson, MA US
Other Locations:
Job Type: Experienced Hire

Engineering Manager - IP Validation

Job Description

The microprocessor has driven the digital revolution, dramatically transforming the way we live, work, and play. As a coherency fabric IP validation manager, you will have an integral role in leading a technical team designing and delivering innovative coherent fabric architectures with rich feature sets to deliver higher levels of performance, energy-efficiency and value that form the computing backbone of the connected world.

In this position, you will be a validation manager in the pre-silicon IP validation team in Intel's Scalable Performance CPU Development Group (SDG).

You will be responsible for validating the CPU coherency fabric design IP for high-end, server-oriented computing products.

Your responsibilities will include but not be limited to:

  • Plans, provides resources for and directs activities in engineering function to meet schedules, standards, and cost.
  • Cultivates and reinforces appropriate group values, norms and behaviors.
  • Identifies and analyzes problems, plans, tasks, and solutions.
  • Provides guidance on employee development, performance, and productivity issues.
  • Plans and schedules daily tasks, uses judgment on a variety of problems requiring deviation from standard practices.
  • First line management of engineers
  • Setting goals, schedule and staging plans along with tracking and enabling execution for team
  • Technical hands-on contributions
  • Contributing to organizations longer-term technical visions

Team's deliverables include:

Validation of server features in cluster test environments

  • Validating designs by:
    • Authoring validation plans
    • Writing focus tests
    • Creating templates defining coverage strategies
    • Developing and analyzing coverage monitors
    • Creating event injectors
    • Writing architectural and micro-architectural correctness checkers
    • Developing BFMs (Bus Functional Model)
    • Running functional simulations
    • Debugging failures to root cause
  • Maintaining and enhancing the validation infrastructure by creating new tools to support validation.

The ideal candidate will be able to demonstrate the following behaviors:

  • Strong leadership skills and drive to guide and motivate team
  • Strong communication skills and ability to influence and work across large teams


BS or MS in EE, CS, or Computer Engineering - 10+ years of hands-on experience and a track-record of success in pre-silicon validation to provide basis for management judgment and schedule management

  • 4 years technical leadership / management experience
  • 3 years of experience of SV OVM/UVM
  • 3 years of experience computer architecture
  • 3 years of experience of validation architecture and infrastructure
  • 3 years of experience of stat of the art coherency protocols and interconnect protocols


Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
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