Inside this Business Group
In support of the high-demand from our customers, the Post Silicon Validation Group is expanding and recruiting new member. This engineering service group is focused on Validation activities to flush bugs out of silicon implementations quickly and efficiently enabling high quality products to be delivered.
A key element of many SOC designs, especially for networking applications, is the high-speed SerDes IP element. It is critical to validate SerDes implementations in the lab to ensure they are functionally correct and meet the performance and other characteristics specified by the IP specification. MIG ACES group placed in Jerusalem is looking for a student for post-silicon validation in a lab environment to test SerDes IP designs
Creating tests in Python language to test SerDes and high-speed analog IO IPs in a lab environment working with an existing automation framework.
Collecting, analyzing and presenting validation results from lab equipment and sharing them with the analog design team and project management.
BS in Electrical Engineering or equivalent, studying toward second degree is an advantage.
Direct experience with SerDes or high-speed IO IP post-silicon validation
Optimizing post-silicon lab automation and environments
Knowledge of Python, or similar scripting language, for post-silicon validation.
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.