Come and join us! Intel is seeking highly qualified candidates to join our Data Center Group (DCG) team as a Digital Design Engineer!
As a Digital Design Engineer, you will develop and support digital circuit design for cell libraries. You will perform custom digital circuit design and simulation as well as design, develop, modify and evaluate digital electronic parts, components or integrated circuitry for use in digital electronic equipment and other hardware systems.
Other responsibilities include, but are not limited to:
-Determines design approaches and parameters.
-Performs digital circuit design, verification and layout, data path design and digital block synthesis.
-Collaborate with the System Architect to review system requirement and provide feedback.
-Micro architect, develop specification and perform detailed logic design at the block level.
-Perform coding, block level verification and work with Verification team to validate the design.
-Support DFT implementation and backend timing closures.
In this position you will gain invaluable experience which will allow growth and expanded opportunities within this business group as well as future possible opportunities with other business groups within Intel.
The Data Center Group (DCG) drives new products technologies from high-end co-processors for supercomputers to low-energy systems for enterprise and the cloud, as well as solutions for big data and intelligent devices. The group is a worldwide organization that develops the products and technologies that power nine of every 10 servers sold worldwide.
Inside this Business Group
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Required Qualifications:
Bachelor degree in Electrical Engineering with 4+ years of industry experience or a Master’s degree in Electrical Engineering with 3+ years of industry experience.
-4 plus years of experience with Micro Architect and RTL coding for high performance, low power design using Verilog.
-4 plus years of experience with Simulation, Lint, CDC and Synthesis using Intel TFM.
Additional Preferred Qualifications:
-Master’s degree or higher preferred.
-Experience with IOSF protocol, PSF fabric, Chassis Prior work in FEC, Equalizer, Digital Filter design is a plus.
-Able to demonstrate innovative and analytical thinking.
-Able to plan and organize day to day activities and execute according to plan.